1. Technical Field of the Invention
This invention relates to a memory controller, and to a method for use in a memory controller, in order to synchronize captured data with a system clock signal.
2. Background of the Invention
In many electronic devices, it is common for a separate memory device to be provided. Data must then be written to, and read from, this separate memory device, by way of a memory interface.
A source synchronous external memory device returns data with its own clock signal, which allows the returned data to be captured with a high degree of accuracy. However, there then remains the problem of resynchronizing the captured data with the clock signal which controls the other components of the electronic device. This can be difficult because, although the clock signal accompanying the returned data is derived originally from the system clock, it is offset by a variable delay.
For example, this time delay depends upon the length of the data paths to and from the memory device. In addition, even in devices which have been manufactured to the same specification, the time delay can vary from one device to another, because of manufacturing process variations. Further, the time delay can vary in use of a single device, because of changes in the supply voltage and/or the operating temperature of the device.
The problem of resynchronization of the captured data with the system clock is particularly acute in the case of high speed memory devices, such as DDR (Double Data Rate) memory devices, and similar memory devices.
One solution to this problem is disclosed in the document ‘DDR SDRAM Controller MegaCore Function User Guide, version 1.2.0’, published by Altera Corporation, at pages 78-86, which describes a timing analysis to resynchronize the captured data with the system clock.
However, it is time consuming to perform this analysis. Further, changes in the time delay resulting from changes in the operating voltage and temperature cannot be compensated in this way.